# Design Rule Verification Report

Date: |  | 2024/12/20 ÐÇÆÚÎå
Time: |  | 13:13:04
Elapsed Time: |  | 00:00:01
Filename: |  | E:\WORK\2024\FL11\FL_INT\FL_Int.PcbDoc

Warnings: |  | 0
Rule Violations: |  | 0

## Summary

Warnings | Count
--- | ---
Total | 0

Rule Violations | Count
--- | ---
Clearance Constraint (Gap=3mil) (All),(All) | 0
Short-Circuit Constraint (Allowed=No) (All),(All) | 0
Un-Routed Net Constraint ( (All) ) | 0
Modified Polygon (Allow modified: No), (Allow shelved: No) | 0
Width Constraint (Min=3mil) (Max=50mil) (Preferred=8mil) (All) | 0
Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) | 0
Hole Size Constraint (Min=1mil) (Max=100mil) (All) | 0
Hole To Hole Clearance (Gap=1mil) (All),(All) | 0
Minimum Solder Mask Sliver (Gap=0mil) (All),(All) | 0
Silk To Solder Mask (Clearance=0mil) (IsPad),(All) | 0
Silk to Silk (Clearance=0mil) (All),(All) | 0
Net Antennae (Tolerance=0mil) (All) | 0
Matched Lengths(Tolerance=1000mil) (InDifferentialPair ('CLK')) | 0
Matched Lengths(Tolerance=1000mil) (InDifferentialPair ('CLK')) | 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) | 0
Total | 0