Protel Design System Design Rule Check
PCB File : E:\WORK\2024\FL11\FL_INT\FL_Int.PcbDoc
Date     : 2024/12/20 ÐÇÆÚÎå
Time     : 13:13:04

Processing Rule : Clearance Constraint (Gap=3mil) (All),(All)
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0

Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0

Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
Rule Violations :0

Processing Rule : Width Constraint (Min=3mil) (Max=50mil) (Preferred=8mil) (All)
Rule Violations :0

Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)
Rule Violations :0

Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (All)
Rule Violations :0

Processing Rule : Hole To Hole Clearance (Gap=1mil) (All),(All)
Rule Violations :0

Processing Rule : Minimum Solder Mask Sliver (Gap=0mil) (All),(All)
Rule Violations :0

Processing Rule : Silk To Solder Mask (Clearance=0mil) (IsPad),(All)
Rule Violations :0

Processing Rule : Silk to Silk (Clearance=0mil) (All),(All)
Rule Violations :0

Processing Rule : Net Antennae (Tolerance=0mil) (All)
Rule Violations :0

Processing Rule : Matched Lengths(Tolerance=1000mil) (InDifferentialPair ('CLK'))
Rule Violations :0

Processing Rule : Matched Lengths(Tolerance=1000mil) (InDifferentialPair ('CLK'))
Rule Violations :0

Processing Rule : Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
Rule Violations :0


Violations Detected : 0
Waived Violations : 0
Time Elapsed        : 00:00:01